User`s manual

32
T1
B
A23 to A0
RD/
RD/
RD/
D15 to D0
T2 T3
When written
t
AD
t
AS1
t
AH1
t
RSD1
t
RDS1
t
RDH1
t
RSD2
t
RDS2
t
RDH2
t
ASD
t
ASD
t
RSD1
t
RSD1
t
AC6
t
AC4
t
AA5
t
AS2
t
WDD
t
WSW2
t
WDH1
t
WDS1
t
WRD1
t
WRD2
t
AH1
t
AA4
t
AS1
t
AS1
t
RWD
t
CSD1
When read
(RDNn 1)=
When read
(RDNn =0)
D15 to D0
(When written)
t
RWD
t
RWD
t
BSD
t
BSD
t
RWD
t
RWD
t
RWD
D15 to D0
φ
to
and
Figure 3.2 Basic Bus Cycle (Software Wait)
The delay time is generated on the timing of the _RES and _NMI signals when they are input to the evaluation
chip from the user system, as shown in table 3.3, because this connection for those signals is via logic circuit on
the evaluation chip board.
Table 3.3 Delay Time for Signal Connected via the Evaluation Chip Board
Signal Name Delay Time (ns)
_RES 18
_NMI 18
_STBY 16