User`s manual

146
5.6.3 On-Emulator Break
• A break will occur several cycles after a condition is satisfied.
• The states of IRQ15 to IRQ0 are ORed and this result is applied as the IRQ condition.
• The address and data conditions are satisfied on the bus cycles where the values on the address bus or data
bus match. Consider the following points when setting these conditions.
• Longword access
Longword data is read and written in a single bus cycle. A data condition is only valid for a longword
access when specified as longword. When a specified address is not a multiple of four (4n), several
cycles will be generated as shown in tables 5.4 and 5.5. Set address and data conditions according to
these tables. Note that longword data is only valid as the size of an access.
• Word access
Word data is read and written in a single bus cycle. Word data is only valid as the size of an access.
When a specified address is not a multiple of two (2n), several cycles will be generated as shown in
tables 5.4 and 5.5. Set address and data conditions according to these tables. Note that word data is
only valid as the size of an access.
• Byte access
Byte data is read and written in a single bus cycle. A data condition is only valid for a byte access
when specified as byte. Any address condition, whether an even or odd address, is valid.
Use the mask function so that no invalid data of a 32-bit data bus will be applied as a condition to search data.