User`s manual

145
5.6 Event Functions
5.6.1 Software Breakpoints
• A software breakpoint is accomplished by replacing the instruction at the specified address with a special
instruction. Accordingly, it can only be set to the RAM area including the emulation memory. However, it
cannot be set to the following addresses:
⎯ An address whose memory content is H'5770
⎯ Areas other than the CS areas (except for the on-chip ROM and RAM areas)
• Do not modify the contents of the software breakpoints addresses by the user program.
• The content of a software breakpoint address is replaced by a break instruction during user program
execution.
• The maximum number of software breakpoints and temporary PC breakpoints in [Temporary PC
Breakpoints] of the [Run Program] dialog box is 255 in total. Therefore, when 255 software breakpoints
have been set, no temporary breakpoint set in [Temporary PC Breakpoints] of the [Run Program] dialog box
is valid. Ensure that the total number of software breakpoints and temporary PC breakpoints is 255 or less.
• The [Go To Cursor] function, which can be selected from the [Debug] menu or the popup menu after the
mouse cursor is positioned on the target address in the [Editor] window, is implemented by a software
breakpoint. Accordingly, when 255 software breakpoints have been set, this function is not available.
• Do not set a breakpoint immediately after a delayed branch instruction (at a slot instruction). If this is
attempted, a slot illegal instruction interrupt will occur when the delayed branch instruction is executed, and
the break will not occur.
5.6.2 On-Chip Break
• The satisfaction count can only be set for channel 4.
• A data bus condition can only be set for channel 4.
• The address and data conditions are satisfied on the bus cycles where the values on the address bus or data
bus match. Consider the following points when setting these conditions.
• Longword access
Longword data is read and written in a single bus cycle. A data condition is only valid for a longword
access when specified as longword. When a specified address is not a multiple of four (4n), several
cycles will be generated as shown in tables 5.4 and 5.5. Set address and data conditions according to
these tables. Note that longword data is only valid as the size of an access.
• Word access
Word data is read and written in a single bus cycle. Word data is only valid as the size of an access.
When a specified address is not a multiple of two (2n), several cycles will be generated as shown in
tables 5.4 and 5.5. Set address and data conditions according to these tables. Note that word data is
only valid as the size of an access.
• Byte access
Byte data is read and written in a single bus cycle. A data condition is only valid for a byte access
when specified as byte. Any address condition, whether an even or odd address, is valid.