User`s manual

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5.4.3 Parallel Access Function
The parallel access function is implemented by the DTC channels specialized for the debugger, which are not
user resources. However, because the DTC channels are included in the user-resource DTC module, the parallel
access function may not be available in the following cases depending on the state of the target MCU or the
emulator settings:
• When the DTC module is in the module stop state, the parallel access function is not available.
• When the priority of the DTC is lower than that of the CPU, the parallel access function is not available.
• In the software standby mode, the parallel access function is not available.
• When there is a conflict between a parallel access and a reset, the parallel access fails.
• When there is a conflict between a parallel access and an NMI interrupt, the parallel access fails. Bit 0 and
the transfer stop flag (ERR) of the DTC control register (DTCCR) are set.
• When an address error occurs during a parallel access, the parallel access fails. Bit 0 and the transfer stop flag
(ERR) of the DTC control register (DTCCR) are set.
• When [Enable DTC parallel access] is disabled in the [Configuration Properties] dialog box, the parallel
access function is not available.
• When the profiling function is used, the parallel access function during user program execution is not
available.
If a parallel access to read memory fails or a parallel access is attempted under the condition where the parallel
access function is not available, incorrect memory contents will be displayed. If a parallel access to write to
memory fails, incorrect values will be written to.
If the message [Parallel Access Error] appears on the [Debug] sheet of the [Output] window when a parallel
access fails, parallel accesses will be disabled until a break occurs.
If the parallel access function is not necessary or is not available, clear [Enable DTC parallel access] in the
[Configuration Properties] dialog box to avoid unnecessary accesses.
5.5 Executing Your Program
5.5.1 Step Execution
Break conditions are ignored during step execution, but triggers will be output.