User`s manual

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3.5.5 Port Registers (PORTx) ⎯Restriction
(1) When the module pins are used as inputs
In the emulator, undefined values are read from PORTx corresponding to the modules. In the actual MCU,
however, reading PORTx allows reading the states of the pins.
(2) When the module pins are used as outputs
In the emulator, undefined values are read from PORTx corresponding to the modules when the value of the
data direction registers is 0. In the actual MCU, however, reading PORTx allows reading the states of the
pins.
Peripheral modules that apply: Motor-control PWM timer, 16-bit PWM, RCAN, SSU, SDG, and DA
3.5.6 Input Buffer Control Register (PnICR) ⎯Restriction
In the emulator, pins can be used as inputs for the peripheral modules mentioned above regardless of the setting
of the corresponding ICR bits.
In the actual MCU, however, the input buffers are invalid and the input signals are fixed high for pins where the
corresponding ICR bit has been cleared to 0. A pin cannot be used as an input for a peripheral module unless the
corresponding ICR bit is set to 1.
If you are using any of these modules, ensure that your program sets the ICR bits for the corresponding pins to 1
before the module is used.
Peripheral modules that apply: SSU and RCAN
3.5.7 Watch Timer (WAT) ⎯Restriction
In the emulator, resetting the WDT initializes the WAT registers. In the actual MCU, the WAT registers are not
initialized.
3.5.8 Port Function Control Register 4 (PFCR4) ⎯Note
In the emulator, the value of PFCR4 is H’1F in the on-chip ROM disabled mode and A23 to A21 are not output
as addresses. In the MCU, however, the value of PFCR4 is H’FF in the on-chip ROM disabled mode. To use
A23 to A21 in the emulator, the user program must write the value H’FF to address H’FFFFFBC4.
3.5.9 Access to the Internal RAM ⎯Note
In the emulator, writing to the internal RAM takes one cycle by default. To make the emulator write data to the
RAM in two cycles, the user program must write the value H’35 to address H’FFFFFD97
before any RAM
access. After that, the RAM should not be accessed for at least one cycle. This address will be reinitialized
whenever the reset pin is activated (goes low). In such cases, write the value H’35 to the same address again
after the system has been released from the reset state.
3.5.10 External Expanded Mode ⎯Restrictions
1. When the frequency of Bφ (external bus clock) is 20 MHz or higher, external accesses must be made in 3 or
more state cycles.
2. While the emulator is operating in the external expanded mode, disabling output of Bφ prevents external
accesses.
3. The emulator starts output of the write data at the rising edge of the T2 cycle. The actual MCU, however,
starts output of data at the falling edge of the T1 cycle.