User`s manual

ManualsBrandsRenesas ManualsServerHEW Target

QDK™

Renesas RX with HEW

state-machine.com/rx

(8) --QK_intNest_; \

(9) if (QK_intNest_ == (uint8_t)0) { \

(10) uint8_t p = QK_schedPrio_(); \

(11) if (p != (uint8_t)0) { \

(12) set_psw((unsigned long)0); \

(13) QK_schedExt_(p); \

} \

(14) restore_acc(&acc_); \

} while (0)

(15) #define QK_EXT_SAVE(act_) \

(16) ((act_)->thread = (void *)get_fpsw())

(17) #define QK_EXT_RESTORE(act_) \

(18) set_fpsw((unsigned long)(act_)->thread)

#include <machine.h> /* for intrinsics set_ipl()/get_fpsw()/set_fpsw() */

#include "qk.h" /* QK platform-independent public interface */

(1) The

QK_ISR_ENTRY()

macro must be invoked at the entry to the ISR code and definitely before any

QP services.

(2) The storage for the RX Accumulator is allocated on the stack.

(3) The RX Accumulator is saved.

(4) With interrupts still disabled, the QK interrupt nesting level is incremented to account for entering

another level of interrupt. (The QK interrupt nesting level is decremented and checked on ISR exit,

discussed later.)

(5) Interrupts are enabled via a compiler intrinsic function (remember that RX CPU enters the ISR with

interrupts disabled). Note that this only sets PSW[I] = 1 (enabled); it does not adjust the PSW[IPL],

the processor's interrupt priority level. Only interrupts with a priority greater than the current IPL

value may preempt this ISR.

(6) The

QK_ISR_EXIT()

macro and must be the last line of a user-written ISR in C. The macro performs

"exit ISR housekeeping" and transfers control to the QK scheduler if necessary.

(7) Interrupts are disabled (PSW[I] set to 0) in order to safely adjust the interrupt nesting level.

(8) The QK interrupt nesting level is decrement to account for leaving the interrupt. When the interrupt

nesting value becomes 0, this indicates that the code is about to return to task level.

(9-11) The

QK_schedPrio_()

function returns the highest priority task ready to run or zero if no task

has a higher priority than the current level.

(12) The Interrupt Priority Level in the Program Status Word register (PSW[IPL]) is set to 0, which

corresponds to the task level priority. This is exactly what is described in [PSiCC2], Figure 10.2,

item (6); setting IPL to zero corresponds to executing an "End of Interrupt" instruction, which means

that the interrupt controller of the RX CPU stops prioritizing the current interrupt. At this point, the

interrupt controller will allow any interrupt to run, which is exactly the behavior expected at task level.

(13) The extended QK scheduler is invoked to keep launching the high-priority tasks as long as they are

above the currently serviced priority (see [PSiCC2], Figure 10.2, items (6) through (8)). The QK

scheduler is designed to be called with with interrupts disabled and also returns with interrupts

disabled, although it enables interrupts before launching any task.

24 of 32