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Renesas RX with HEW

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/* inline definitions */

(10) #pragma inline_asm clr_psw_i

(11) static void clr_psw_i(void) { CLRPSW I }

(12) #pragma inline_asm set_psw_i

(13) static void set_psw_i(void) { SETPSW I }

#include "qep_port.h" /* QEP port */

#include "qvanilla.h" /* "Vanilla" cooperative kernel */

#include "qf.h" /* QF platform-independent public interface */

(1) The

QF_MAX_ACTIVE

macro specifies the maximum number of active object priorities in the

application. You always need to provide this constant. Here,

QF_MAX_ACTIVE

is set to the maximum

limit of 63 active object priorities in the system. You can decrease this number to reduce the RAM

footprint of the QF framework.

(2) The

QF_MAX_EPOOL

macro specifies the maximum number of event pools in the application.

(3) The

QF_INT_DISABLE()

macro resolves to the function

clr_psw_i()

, which is defined in inline

assembly as

"CLRPSW I

". This single instruction clears PSW[I] in the PSW register, thereby

disabling all interrupts.

(4) The

QF_INT_ENABLE()

macro resolves to the function

set_psw_i()

, which is defined in inline

assembly as

"SETPSW I

". This single instruction sets PSW[I] in the PSW register, thereby enabling

all interrupts.

(5) The

QF_CRIT_STAT_TYPE

macro is not defined, which means that the simple critical section policy of

“unconditional interrupt locking and unlocking” is applied.

(6) The

QF_CRIT_ENTRY()

macro does not use its parameter in this case and simply unconditionally

disables interrupts.

(7) The

QF_CRIT_EXIT()

macro does not use its parameter in this case and simply unconditionally re-

enables interrupts.

NOTE: The simple and very efficient critical section policy does not allow nesting of critical sections.

However, the RX interrupt handlers disable interrupts upon entry, so the body of the ISR becomes a

critical section. To avoid nesting of critical sections, interrupts must be enabled before calling any QP

service from an ISR. This enabling interrupts after entry to the ISR and disabling interrupts before exit

is accomplished in the macros

QF_ISR_ENTRY()

QF_ISR_EXIT()

described below.

(8) To avoid nesting of critical sections, the macro

QF_ISR_ENTRY()

must be called at the beginning of

every ISR before invoking any QP services. This macro re-enables interrupts (i.e., permit interrupt

nesting and preemption of the current ISR by higher-priority interrupts). Please note, however that

the prioritized interrupt controller of the RX CPU prevents any interrupts of lower or equal priority

from preempting the currently serviced interrupt level.

NOTE: If you don't wish interrupts to be able to preempt each other, you can always assign the same

priorities to all interrupts.

(9) The macro

QF_ISR_EXIT()

must be used at the very end of every ISR. This clears the CPU's

PSW[I] bit to 0, just as it was when the ISR was entered.

(10-11) The Renesas RX compiler requires this unusual syntax to define the inline assembly function

clr_psw_i()

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