User`s manual

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QDK™
Renesas RX with HEW
state-machine.com/rx
3.5 RX CPU Interrupt Processing (Software)
The Renesas RX compiler, as most embedded cross-compilers, can generate interrupt service routines
(ISRs), which are designated with the special #pragma interrupt (see Listing 2). The Renesas compiler
can also automatically populate the RX vector table with the address of the ISR, when you provide the
vector number by means of the #pragma vect=... attribute. The HEW project wizard generates the
declarations of all the interrupts in the file vect.h header file.
Listing 2: Declaring an interrupt function with Renesas RX compiler (file vect.h )
#pragma interrupt (Excep_CMTU0_SMT0(vect=28))
void Excep_CMTU0_SMT0(void);
NOTE: An interrupt function must have the return type void, and it cannot specify any parameters.
You can define your own interrupt functions in the module intprog.c . The following Listing 3 shows the
definition of the Excep_CMTU0_SMT0() interrupt service routine.
Listing 3: Defining an interrupt function with Renesas RX compiler (file intprog.c )
#pragma interrupt (Excep_CMTU0_SMT0(vect=28))
void Excep_CMTU0_CMT0(void) {
QF_ISR_ENTRY(); /* inform the QF Vanilla kernel about entering the ISR */
#ifdef Q_SPY
QS_tickTime_ += QS_tickPeriod_; /* account for the clock rollover */
#endif
QF_TICK(&Excep_CMTU0_CMT0); /* process all armed time events */
QF_ISR_EXIT(); /* inform the QF Vanilla kernel about exiting the ISR */
}
In case of the RX processor, such compiler-generated ISRs are perfectly suitable for the QP framework
(including both the cooperative “Vanilla” kernel and the preemptive QK kernel), but in case of the QK
kernel special care must be taken to preserve all the registers possibly used by the tasks. Also, for any
kind of kernel, you need to understand which registers are and, more importantly, aren't saved and
restored by the compiler, so that you know which operations are not allowed in the ISR code.
The Renesas compiler-generated #pragma interrupt function saves and restores any general-purpose
registers clobbered by this function and returns with the RTE instruction. However, the interrupt function
does not save the Accumulator or the FPSW registers.
NOTE: This means that the ISR cannot perform any operations that clobber the Accumulator or the
FPSW register, such as the multiply, multiply-and-accumulate instructions; EMUL , EMULU , FMUL, MUL ,
and RMPA , or any floating-point instructions in which case the prior value in the accumulator and/or
the FPSW register is modified by execution of the instruction.
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