User`s manual

QDK™

Renesas RX with HEW

state-machine.com/rx

The PSW has an interrupt control bit (PSW[I], bit 16) that globally enables (PSW[I] = 1) or disables

(PSW[I] = 0) interrupts. Furthermore, a 4-bit field called Interrupt Priority Level (PSW[IPL], bits 24-27)

reflects the current interrupt priority level. All interrupts to the CPU are assigned a priority of 0-15, with 0

being the lowest priority, and 15 being the highest priority. When PSW[I] = 1 (interrupts are enabled), any

interrupt with a priority higher than the current IPL will interrupt the CPU. Interrupts of a priority less than

or equal to the current IPL value are kept pending until the IPL drops.

NOTE:The RX610 series only has a 3-bit IPL field (values 0-7); bit 27 is reserved, writes are ignored.

At reset, PSW[I] = 0 (interrupts disabled) and PSW[IPL] = 0 (lowest priority level).

3.2 RX CPU Modes

The RX CPU supports two processor modes: Supervisor and User. Each processor mode imposes a level

on rights of access to memory and the instructions that can be executed. Supervisor mode carries greater

rights than user mode and this initial mode out of reset. All QP ports to RX CPU run exclusively in the

Supervisor mode.

3.3 RX CPU Stacks

The RX stack pointer (R0) can be either the interrupt stack pointer (ISP) or the user stack pointer (USP),

depending on the value of the stack pointer select bit (U) in the processor status word (PSW). All QP

ports to RX CPU use exclusively the interrupt stack pointer (ISP) and the user stack pointer is not

used at all. Consequently, the user stack size should be set to zero to prevent wasting of RAM.

3.4 RX CPU Interrupt Processing (Hardware)

The RX family features a sophisticated interrupt control unit (ICU) and a prioritized hardware interrupt

scheme that is a perfect fit for the QP's single-stack, run-to-completion execution architecture. Figure 10

shows the parts of the exception processing handled automatically by the hardware and the parts handled

by the software.

As shown in Figure 10, the hardware processing includes the following steps executed atomically:

1. The exception is acknowledged/accepted by the processor

2. The processor status word (PSW) is stacked automatically

3. PSW[I] is cleared, disabling interrupts

NOTE: The RX processor disables interrupts automatically and atomically in hardware as part of the

interrupt entry sequence.

4. The program counter (PC) of the next instruction (after returning from interrupt) is stacked

automatically

5. PSW[IPL] is set to the priority of the current interrupt

6. The PC is loaded with the vector from the vector table, and execution of the service routine begins

NOTE:The RX processor supports also the concept of a fast interrupt, which uses the backup PC

(BPC) and the backup PSW (BPSW) registers instead of the stack for preserving the PC and the

PSW, respectively.

The fast interrupt can be used with the cooperative “Vanilla” kernel, but should not be used with the

preemptive QK kernel, because it does not use the machine's natural stack protocol.

14 of 32