Datasheet

872
Table C.5 Pin Settings for Multiplex I/O Space
16-Bit Space
Pin Name 8-Bit Space Upper Byte Lower Byte Word/Longword
CS0CS2 HH H H
CS3 LL L L
RAS
*
1
HH H H
CASHH
*
2
HH H H
CASHL
*
2
HH H H
CASLH
*
2
HH H H
CASLL
*
2
HH H H
RD/WR H H H H
AH Valid Valid Valid Valid
RD RL L L L
WH H H H
WRHH RH H H H
WH H H H
WRHL RH H H H
WH H H H
WRH RH H H H
WH L H L
WRL RH H H H
WL H L L
A21–A0 Address Address Address Address
D31–D24 High-Z High-Z High-Z High-Z
D23–D16 High-Z High-Z High-Z High-Z
D15–D8 High-Z Address/Data Address Address/Data
D7–D0 Address/Data Address Address/Data Address/Data
Notes: 1. R: Read, W: Write
2. Valid: High output in accordance with AH timing.
*1 L asserted in RAS down mode or refresh mode.
*2 L asserted in refresh mode.