Datasheet

871
Table C.4 Pin Settings for Normal External Space (cont)
32-Bit Space
Pin Name MSB 2nd Byte 3rd Byte LSB
Upper
Word
Lower
Word Longword
CS0–CS3 Valid Valid Valid Valid Valid Valid Valid
RAS
*
1
HHHHHHH
CASHH
*
2
HHHHHHH
CASHL
*
2
HHHHHHH
CASLH
*
2
HHHHHHH
CASLL
*
2
HHHHHHH
RD/WR H H H H H H H
AH LLLLLLL
RD RLLLLLLL
WHHHHHHH
WRHH RHHHHHHH
WL H H H L H L
WRHL RHHHHHHH
WH L H H L H L
WRH RHHHHHHH
WH H L H H L L
WRL RHHHHHHH
WH H H L H L L
A21–A0 Address Address Address Address Address Address Address
D31–D24 Data High-Z High-Z High-Z Data High-Z Data
D23–D16 High-Z Data High-Z High-Z Data High-Z Data
D15–D8 High-Z High-Z Data High-Z High-Z Data Data
D7–D0 High-Z High-Z High-Z Data High-Z Data Data
Notes: 1. R: Read, W: Write
2. Valid: Chip select signal corresponding with accessed area is low; chip select signal in
other cases is high.
*1 L asserted in RAS down mode or refresh mode.
*2 L asserted in refresh mode.