Datasheet

869
Table C.3 Pin Settings for On-Chip Peripheral Modules
On-Chip Peripheral Module
16-Bit Space
Pin Name
On-Chip
ROM
On-Chip
RAM 8-Bit Space
Upper
Byte
Lower
Byte
Word/
Longword
CS0–CS3 HHH HHH
RAS
*
1
HHH HHH
CASHH
*
2
HHH HHH
CASHL
*
2
HHH HHH
CASLH
*
2
HHH HHH
CASLL
*
2
HHH HHH
RD/WR H H H H H H
AH LLL LLL
RD RH HH HHH
W— HH HHH
WRHH RH HH HHH
W— HH HHH
WRHL RH HH HHH
W— HH HHH
WRLH RH HH HHH
W— HH HHH
WRLL RH HH HHH
W— HH HHH
A21–A0 Address Address Address Address Address Address
D31–D24 High-Z High-Z High-Z High-Z High-Z High-Z
D23–D16 High-Z High-Z High-Z High-Z High-Z High-Z
D15–D8 High-Z High-Z High-Z High-Z High-Z High-Z
D7–D0 High-Z High-Z High-Z High-Z High-Z High-Z
Notes: R: Read, W: Write
*1 L asserted in RAS down state or refresh state.
*2 L asserted in refresh state.