Datasheet

856
Din
Standby
SLEEP
Bus right
release
PD31/
D31/
ADTRG
PDW
RES
R
QD
C
PD31DR
PDR
Dn
Dout
Single
mode
MCU mode 1
MCU mode 0
MCU mode 2
PFC
SBYCR
Q HIZ
QPD31MD0
QPD31MD1
QPD31IOR
A/D
ADTRG
Internal
data bus
PDR: Port D read signal
PDW: Port D write signal
RES: Reset signal
Dout: Data output timing signal
Din: Data bus input timing signal
Figure B.31 PD31/D31/ADTRG Block Diagram