Datasheet

854
Din
Standby
SLEEP
Bus right
release
PDn/
Dn/
CSm
PDW
RES
R
QD
C
PDnDR
PDR
Dn
Dout
Single
mode
MCU mode 1
MCU mode 0
MCU mode 2
PFC
SBYCR
Q HIZ
QPDnMD0
QPDnMD1
QPDnIOR
Internal
data bus
n = 28–29
m = 2–3
PDR: Port D read signal
PDW: Port D write signal
RES: Reset signal
Dout: Data output timing signal
Din: Data bus input timing signal
CSm
Figure B.29 PDn/Dn/CSm Block Diagram (n = 28, 29)