Datasheet

850
Q PDnMD0
Q PDnIOR
Q HIZ
PDR
Dn
RES
PDW
C
D
Q
C
PDnDR
Dout
PFC
SBYCR
Dn
Din
On-chip flash memory
Internal data bus
PDn/Dn
Writer mode
Single mode
MCU mode 0
MCU mode 1
MCU mode 2
Bus right release
Sleep
Standby
n=0–15
PDR: Port D read signal
PDW: Port D write signal
RES: Reset signal
Dout: Data bus output timing signal
Din: Data bus input timing signal
Figure B.25 PDn/Dn Block Diagram (F-ZTAT Version)