Datasheet

844
Q PBnMD0
Q PBnMD1
Q PBnIOR
PBR
A17
RES
PBW
C
D
Q
C
PBnDR
PFC
SBYCR
Q HIZ
CASL,CASH
POE
POEm
INTC
IRQm
PB4/IRQ2/POE2/CASH,
PB3/IRQ1/POE1/CASL
n=3, 4
m=1, 2
PBR: Port B read signal
PBW: Port B write signal
RES: Reset signal
Note: * Only when n = 4.
On-chip flash memory
*
Internal data bus
Writer mode
Standby
Bus right release
Figure B.19 PB4/IRQ2/POE2/CASH,PB3/IRQ1/POE1/CASL
Block Diagram (F-ZTAT Version)