836
PAR
Internal
data bus
RES
CS0, CS1,WRL,
WRH,RD
Single mode
MCU mode 0
MCU mode 1
MCU mode 2
PFC
SBYCR
Standby
Bus right
release
PAW
n = 10-14
PAR: Port A read signal
PAW: Port A write signal
RES: Reset signal
PAnDR
Q
C
D
R
Q PAnMD
Q PAnIOR
Q HIZ
PAn/
XXX
Figure B.11 PAn/XXX Block Diagram
