834
PAR
Internal
data bus
RES
DRAK0
PFC
Standby
PAW
SBYCR
PAR: Port A read signal
PAW: Port A write signal
RES: Reset signal
PA18DR
Q
C
D
R
BSC
BREQ
PA18/
DRAK0/
BREQ
Q PA18IMD1
Q PA18IOR
Q PA18MD0
Q HIZ
Figure B.9 PA18/DRAK0/BREQ Block Diagram
