828
PAR
Internal
data bus
RES
PFC
CS2, CS3
Standby
PAW
PAnDR
Q
C
D
Q PAnMD0
Q PAnMD1
Q PAnIOR
Q HIZ
TCLKA,
TCLKB
SBYCR
MTU
n = 6, 7
PAR: Port A read signal
PAW: Port A write signal
RES: Reset si
nal
R
PA6/
TCLKA/
CS2,
PA7/
TCLKB/
CS3
Figure B.3 PA6/TCLKA/CS2, PA7/TCLKB/CS3 (ZTAT, Mask) Block Diagram
