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Appendix B Block Diagrams
PAR
Internal
data bus
RES
PFC
Standby
PAW
PAnDR
Q
R
C
D
Q PAnMD
Q PAnIOR
SBYCR
RXDm
Q HIZ
SCI
n = 0, 3
m = 0, 1
PAR: Port A read signal
PAW: Port A write signal
RES: Reset signal
PAn/
RXDm
Figure B.1 PAn/RXDm Block Diagram