809
ADF
t
D
t
SPL
t
CONV
t
D
t
SPL
t
CONV
: ADCSR write cycle
: ADCSR address
: A/D conversion start delay time
: Input sampling time
: A/D conversion time
Address
Write signal
Input sampling
timing
CK
(1)
(2)
Legend:
(1)
(2)
Figure 26.32 Analog Conversion Timing
