Datasheet

800
26.3.4 Direct Memory Access Controller Timing
Table 26.8 Direct Memory Access Controller Timing (Conditions: V
CC
= 3.0
*
to 3.6V, AV
CC
= 3.0
*
to 3.6V, AV
CC
= V
CC
± 10%, AV
ref
= 3.0
*
to AV
CC
, V
SS
= AV
SS
= 0V, T
a
=
–20 to +75°C)
Item Symbol Min Max Unit Figure
DREQ0, DREQ1 setup time t
DRQS
35 — ns 26.20
DREQ0, DREQ1 hold time t
DRQH
35 — ns
DREQ0, DREQ1 pulse width t
DRQW
1.5 — t
cyc
26.21
DRAK output delay time t
DRAKD
— 35 ns 26.22
Note: * SH7042/43 ZTAT (excluding A mask) are 3.2V.
CK
t
DRQS
t
DRQS
t
DRQS
t
DRQH
DREQ0
DREQ1
Level clear
DREQ0
DREQ1
Level
DREQ0
DREQ1
Edge
Figure 26.20 DREQ0 and DREQ1 Input Timing (1)