Datasheet

796
CK
A21–A0
Tp Tpw Tr Trw Tc1 Tcw1 Tcw2 Tc2
t
AD
t
AD
t
ASR
t
RASD1
t
RAH
t
RP
t
CASD1
t
CAC
t
AA
t
RAC
t
RDS
t
RDH
t
CASD2
t
CASD1
t
RWD2
t
RWD1
t
DH
t
DS
t
WDH
t
DACKD1
t
DACKD1
t
WDD
t
RSD1
t
RSD2
t
WSD1
t
WSD2
t
RASD2
t
CASD2
RAS
CASxx
RDWR
D31–D0
CASxx
RDWR
D31–D0
DACKn
RD
WRxx
(During read)
(During read)
(During read)
(During read)
(During write)
(During write)
(During write)
(During write)
Row address
Column address
Note: t
RDH
is specified from fastest negate timing of A21–A0, RAS, and CAS.
Figure 26.13 DRAM Cycle (Normal Mode, 2 Waits, TPC = 1, RCD = 1)
CK
A21–A0
Tp Tpw Tr Trw Tc1 Tcw1 Tcw2 Tcw3 Tc2
t
AD
t
AD
t
RAH
t
ASR
t
RP
t
CASD1
t
CAC
t
AA
t
CASD1
t
RDS
t
CASD2
tRWD2
t
RWD1
t
DS
t
DH
t
WDH
t
DACKD1
t
RSD1
t
WSD1
t
WSD2
t
RSD2
t
DACKD1
t
RASD2
t
CASD2
t
WDD
RAS
CASxx
RDWR
D31–D0
CASxx
RDWR
D31–D0
DACKn
RD
WRxx
(During read)
(During read)
(During read)
(During read)
(During write)
(During write)
(During write)
(During write)
Row address
Column address
t
RASD1
t
RDH
t
RAC
Note: t
RDH
is specified from fastest negate timing of A21–A0, RAS, and CAS.
Figure 26.14 DRAM Cycle (Normal Mode, 3 Waits, TPC = 1, RCD = 1)