Datasheet

794
Tp Tr Tc1 Tc2
t
AD
t
AD
t
ASR
t
RP
t
RASD1
t
RAH
t
CASD1
t
CAC
t
AA
t
RAC
t
RDS
t
RASD2
t
CASD2
t
RDH
t
RWD1
t
CASD2
t
CASD1
t
RWD2
t
WDH
t
DH
t
DS
t
WDD
t
DACKD1
t
DACKD1
t
RSD1
t
RSD2
t
WSD1
t
WSD2
CK
A21–A0
RAS
CASxx
RDWR
D31– D0
D31–D0
CASxx
RDWR
DACKn
RD
WRxx
Note: t
RDH
is specified from fastest negate timing of A21–A0, RAS, and CAS.
(During read)
(During read)
(During read)
(During read)
(During write)
(During write)
(During write)
(During write)
Row address
Column address
Figure 26.11 DRAM Cycle (Normal Mode, No Wait, TPC = 0, RCD = 0)