787
CK
RES
MRES
t
RESf
t
RESW
t
MRESW
t
RESr
t
RESS
t
MRESS
t
MRESS
t
RESS
V
IH
V
IH
V
IH
V
IL
V
IL
V
IL
V
IL
Figure 26.4 Reset Input Timing
t
NMIH
t
NMIS
t
NMIr,
t
NMIf
V
IH
V
IL
t
IRQEH
t
IRQES
V
IH
V
IL
t
IRQLS
CK
NMI
IRQ edge
IRQ level
Figure 26.5 Interrupt Signal Input Timing
