Datasheet

773
25.3.8 Serial Communication Interface Timing
Table 25.12 Serial Communication Interface Timing (Conditions: V
CC
= 5.0 V ± 10%, AV
CC
= 5.0 V ± 10%, AV
CC
= V
CC
± 10%, AV
ref
= 4.5 V to AV
CC
, V
SS
= AV
SS
= 0 V, Ta
= – 20 to +75°C)
Item Symbol Min Max Unit Figure
Input clock cycle t
scyc
4—t
cyc
25.27
Input clock cycle (clock sync) t
scyc
6—t
cyc
Input clock pulse width t
sckw
0.4 0.6 t
scyc
Input clock rise time t
sckr
— 1.5 t
cyc
Input clock fall time t
sckf
— 1.5 t
cyc
Transmit data delay time (clock sync) t
TXD
— 100 ns 25.28
Receive data setup time (clock sync) t
RXS
100 — ns
Receive data hold time (clock sync) t
RXH
100 — ns
t
sckw
t
sckr
t
sckf
t
scyc
SCK0, SCK1
Figure 25.27 Input Clock Timing
t
scyc
t
TXD
t
RXS
t
RXH
SCK0, SCK1
TXD0, TXD1
(Transmit data)
RXD0, RXD1
(Receive data)
Figure 25.28 SCI I/O Timing (Clock Sync Mode)