Datasheet

768
25.3.4 Direct Memory Access Controller Timing
Table 25.8 Direct Memory Access Controller Timing (Conditions: V
CC
= 5.0 V ± 10%,
AV
CC
= 5.0 V ± 10%, AV
CC
= V
CC
± 10%, AV
ref
= 4.5 V to AV
CC
, V
SS
= AV
SS
= 0
V, Ta = – 20 to +75°C)
Item Symbol Min Max Unit Figure
DREQ0 and DREQ1 setup time t
DRQS
18 — ns 25.20
DREQ0 and DREQ1 hold time t
DRQH
18 — ns
DREQ0 and DREQ1 pulse width t
DRQW
1.5 — t
cyc
25.21
DRAK output delay time t
DRAKD
— 18 ns 25.22
CK
t
DRQS
t
DRQS
t
DRQS
t
DRQH
DREQ0
DREQ1
Level clear
DREQ0
DREQ1
Level
DREQ0
DREQ1
Edge
Figure 25.20 DREQ0 and DREQ1 Input Timing (1)