Datasheet
767
CK
RAS
CASxx
RDWR
TRcc
t
RASD2
t
CASD2
t
CSR
t
CASD1
TRp TRr1 TRr2
t
RASD1
TRc
Figure 25.18 Self Refresh
CK
A21–A0
DACKn
Ta1 Ta2 Ta3 Ta4 T1 TW TWo T2
t
AD
t
CSD1
t
CSD2
t
AHD1
t
AHD2
t
RSD2
t
MAH
t
MAD
t
RDS
t
RDH
t
MAH
t
WDD
t
MAD
t
WDH
t
DACKD1
t
DACKD1
t
WTS
t
WTH
t
WTS
t
WTH
t
WSD2
t
WR
t
WRH
t
RSD1
CS3
AH
D15–D0
WAIT
D15–D0
RD
WRxx
(During read)
Address
Address
(During read)
(During write)
(During write)
t
WSD1
Note: t
RDH
is specified from fastest negate timing of A21–A0, CS3, and RD.
Figure 25.19 Address Data Multiplex I/O Space Cycle (1 Software Wait + External Wait)