Datasheet

766
CK
A21–A0
Tp Tr Tc1 Tc2 Tc1 Tc2
t
AD
t
AD
t
ASR
t
RASD1
t
RAH
t
RP
t
CASD1
t
CASD2
t
CASD1
t CASD2
t
RASD2
t
CP
t
AA
t
CAC
t
AA
t
RAC
t
RDS
t
RDH
t
RDS
t
RDH
t
CAC
t
CASD1
t
CASD2
t
CASD1
t
CASD2
t
RWD2
t
RWD1
t
RWD2
t
RWD1
t
DH
t
DS
t
WDD
t
WDH
t
WDD
t
WDH
t
DH
t
DS
t
CP
t
DACKD1
t
DACKD1
t
RSD1
t
WSD1
t
WSD2
t
WSD1
t
WSD2
t
RSD2
t
RSD1
t
RSD2
t
DACKD1
RAS
CASxx
RDWR
D31–D0
CASxx
RDWR
D31–D0
DACKn
RD
WRxx
(During read)
(During read)
(During read)
(During read)
(During write)
(During write)
(During write)
(During write)
Note: t
RDH
is specified from fastest negate timing of A21–A0, RAS, and CAS.
Row address
Column address
Column address
Figure 25.16 DRAM Cycle (High-Speed Page Mode)
CK
RDWR
TRp TRr1 TRr2 TRc TRc
t
RASD1
t
RASD2
t
CASD2
t
CSR
t
CASD1
RAS
CASxx
Figure 25.17 CAS Before RAS Refresh (TRAS1 = 0, TRAS0 = 0)