Datasheet

765
CK
A21A0
Tp Tr Tc1 Tcw1 Tcw2 Tcwo Tc2
t
AD
t
AD
t
ASR
t
RAH
t
RASD1
t
RP
t
CASD1
t
CAC
t
AA
t
RAC
t
RDH
t
CASD2
t
RWD2
t
CASD1
t
WDH
t
DH
t
DS
t
RWD1
t
WDD
t
WTS
t
WTH
t
WTS
t
WTH
t
DACKD1
t
RSD2
t
WSD2
t
WSD1
t
RSD1
t
RASD2
t
DACKD1
t
CASD2
t
RDS
RAS
CASxx
RDWR
D31D0
CASxx
RDWR
D31D0
DACKn
RD
WRxx
WAIT
(During read)
(During read)
(During read)
(During read)
(During write)
(During write)
(During write)
(During write)
Row address
Column address
Note: t
RDH
is specified from fastest negate timing of A21A0, RAS, and CAS.
Figure 25.15 DRAM Cycle (Normal Mode, 2 Waits + Wait due to WAIT Signal)