Datasheet

761
CK
A21–A0
T1 Tw TwoTw T2
t
WTS
t
WTH
t
WTS
t
WTH
CSn
RD
WRxx
WAIT
DACKn
(During read)
(During read)
(During write)
(During write)
D31–D0
D31–D0
Figure 25.10 Basic Cycle (2 Software Waits + Wait due to WAIT Signal)