Datasheet

758
Table 25.7 Bus Timing (Conditions: V
CC
= 5.0 V ± 10%, AV
CC
= 5.0 V ± 10%, AV
CC
= V
CC
±
10%, AV
ref
= 4.5 V to AV
CC
, V
SS
= AV
SS
= 0 V, Ta = – 20 to +75°C)
Item Symbol Min Max Unit Figure
Write address setup time t
AS
0 — ns 25.8–25.9
Write address hold time t
WR
5 — ns 25.8, 25.9, 25.19
Write data hold time t
WRH
0—ns
Read/write strobe delay time 1 t
RWD1
2
*
3
18 ns 25.11–25.16
Read/write strobe delay time 2 t
RWD2
2
*
3
18 ns
High-speed page mode CAS
precharge time
t
CP
t
cyc
– 25 — ns 25.16
RAS precharge time t
RP
t
cyc
× (TPC + 1.5) – 15 — ns 25.11–25.16
CAS setup time t
CSR
10 — ns 25.17, 25.18
AH delay time 1 t
AHD1
2
*
3
18 ns 25.19
AH delay time 2 t
AHD2
2
*
3
18 ns
Multiplex address delay time t
MAD
2
*
3
18 ns
Multiplex address hold time t
MAH
0—ns
DACK delay time t
DACKD1
2
*
3
21 ns 25.8, 25.9, 25.11–
25.16, 25.19
Notes: n is the number of waits. m is 0 when the number of DRAM write cycle waits is 0, and 1
otherwise. RCD is the set value of the RCD bit in DCR. TPC is the set value of the TPC bit
in DCR.
*1 If the access time is satisfied, t
RDS
need not be satisfied.
*2t
WDH
(max) is a reference value.
*3 The delay time Min values are reference values (typ).
*4t
RDS
is a reference value.
*5 When 28.7MHz, tASR=0ns (min)