Datasheet

757
25.3.3 Bus Timing
Table 25.6 Bus Timing (Conditions: V
CC
= 5.0 V ± 10%, AV
CC
= 5.0 V ± 10%, AV
CC
= V
CC
±
10%, AV
ref
= 4.5 V – AV
CC
, V
SS
= AV
SS
= 0 V, Ta = – 20 to +75°C)
Item Symbol Min Max Unit Figure
Address delay time t
AD
2
*
3
18 ns 25.8, 25.9,
25.11–25.16,
25.19
CS delay time 1 t
CSD1
2
*
3
21 ns 25.8, 25.9,
25.19
CS delay time 2 t
CSD2
2
*
3
21 ns
Read strobe delay time 1 t
RSD1
2
*
3
18 ns 25.8, 25.9,
Read strobe delay time 2 t
RSD2
2
*
3
18 ns
25.11–25.16,
Read data setup time t
RDS
*
4
15 ns
25.19
Read data hold time t
RDH
0—ns
Write strobe delay time 1 t
WSD1
2
*
3
18 ns
Write strobe delay time 2 t
WSD2
2
*
3
18 ns
Write data delay time t
WDD
—35ns
Write data hold time t
WDH
010
*
2
ns
WAIT setup time t
WTS
15 ns 25.10, 25.15,
WAIT hold time t
WTH
0—ns
25.19
RAS delay time 1 t
RASD1
2
*
3
18 ns 25.11–25.18
RAS delay time 2 t
RASD2
2
*
3
18 ns
CAS delay time 1 t
CASD1
2
*
3
18 ns
CAS delay time 2 t
CASD2
2
*
3
18 ns
Read data access time t
ACC
*
1
t
cyc
× (n + 2) – 40 ns 25.8, 25.9
Access time from read strobe t
OE
*
1
t
cyc
× (n + 1.5) – 40 ns
Access time from column
address
t
AA
*
1
t
cyc
× (n + 2) – 40 ns 25.11–25.16
Access time from RAS t
RAC
*
1
t
cyc
× (n + RCD + 2.5) – 40 ns
Access time from CAS t
CAC
*
1
t
cyc
× (n + 1) – 40 ns
Row address hold time t
RAH
t
cyc
× (RCD + 0.5) – 15 ns
Row address setup time t
ASR
*
5
t
cyc
× 0.5–17.5 ns
Data input setup time t
DS
t
cyc
× (m + 0.5) – 25 ns
Data input hold time t
DH
20 ns