Datasheet

743
Section 24 Power-Down State
24.1 Overview
In the power-down state, the CPU functions are halted. This enables a great reduction in power
consumption.
24.1.1 Power-Down States
The power-down state is effected by the following two modes:
• Sleep mode
• Standby mode
Table 24.1 describes the transition conditions for entering the modes from the program execution
state as well as the CPU and peripheral function status in each mode and the procedures for
canceling each mode.
Table 24.1 Power-Down State Conditions
State
Mode
Entering
Procedure Clock CPU
On-Chip
Peripheral
Modules
CPU
Registers RAM
I/O
Ports
Canceling
Procedure
Sleep Execute SLEEP
instruction with
SBY bit set to 0
in SBYCR
Run Halt Run Held Held Held
• Interrupt
• DMAC/DTC
address error
• Power-on
reset
• Manual reset
Stand-
by
Execute SLEEP
instruction with
SBY bit set to 1
in SBYCR
Halt Halt Halt
*
1
Held Held Held or
high
impe-
dance
*
2
• NMI interrupt
• Power-on
reset
• Manual reset
Notes: SBYCR: standby control register. SBY: standby bit
*1 Some bits within on-chip peripheral module registers are initialized by the standby
mode; some are not. Refer to table 24.3, Register States in the Standby Mode, in
section 24.4.1, Transition to Standby Mode. Also refer to the register descriptions for
each peripheral module.
*2 The status of the I/O port in standby mode is set by the port high impedance bit (HIZ) of
the SBYCR. Refer to section 24.2, Standby Control Register (SBYCR). For pin status
other than for the I/O port, refer to Appendix C, Pin Status.