Datasheet

38
Table 1.7 Pin Functions (cont)
Classification Symbol I/O Name Function
Operating
mode control
MD0–MD3 I Mode set Determines the operating mode. Do
not change input value during
operation.
FWP I Flash memory
write protect
Protects flash memory from being
written or deleted.
Interrupts NMI I Non-maskable
interrupt
Non-maskable interrupt request pin.
Enables selection of whether to
accept on the rising or falling edge.
IRQ0–
IRQ7
I Interrupt
requests 0–7
Maskable interrupt request pins.
Allows selection of level input and
edge input.
IRQOUT O Interrupt request
output
Indicates that interrupt cause has
occurred. Enables notification of
interrupt generation also during bus
release.
Address bus A0–A21 O Address bus Outputs addresses.
Data bus D0–D15
(QFP-112)
D0–D31
(QFP-144)
I/O Data bus 16-bit (QFP-112 pin and TQFP-120
pin versions) or 32-bit (QFP-144 pin
version) bidirectional data bus.
Bus control CS0–CS3 O Chip selects 0–3 Chip select signals for external
memory or devices.
RD O Read Indicates reading from an external
device.
WRH O Upper write Indicates writing the upper 8 bits
(15–8) of external data.
WRL O Lower write Indicates writing the lower 8 bits
(7–0) of external data.
WAIT I Wait Input causes insertion of wait cycles
into the bus cycle during external
space access.
RAS O Row address
strobe
Timing signal for DRAM row
address strobe.
CASH O Upper column
address strobe
Timing signal for DRAM column
address strobe.
Output when the upper 8 bits of
data are accessed.