Datasheet

716
AND.B #ECLEAR,@(R0,GBR) ; Clear E
EWait_4 SUBC R2,R3 ; Wait 10 µs
BF EWait_4
;
MOV.L #Wait10u,R3
AND.B #ESUCLEAR,@(R0,GBR) ; Clear ESU
EWait_5 SUBC R2,R3 ; Wait 10 µs
BF EWait_5
;
MOV.L #WDT_TCSR,R1 ; Disable WDT
MOV.W #H’A55F,R3
MOV.W R3,@R1
;
MOV.L #Wait20u,R3
OR.B #EVSET,@(R0,GBR) ; Set EV
EWait_6 SUBC R2,R3 ; Wait 20 µs
BF EWait_6
;
MOV.L @R5,R6 ; Erase memory block start address -> R6
BlockVerify_1 .EQU $ ; Erase-verify
MOV.L #H’FFFFFFFF,R8
MOV.L R8,@R6 ; H'FF dummy write
MOV.L #Wait2u,R3
EWait_7 SUBC R2,R3
BF EWait_7
;
MOV.L @R6+,R1 ; Read verify data
CMP/EQ R8,R1
BF BlockVerify_NG
MOV.L @(8,R5),R7
CMP/EQ R6,R7 ; Check for last address of memory block
BF BlockVerify_1
MOV.L #Wait5u,R3
AND.B #EVCLEAR,@(R0,GBR) ; Clear EV
EWait_8 SUBC R2,R3 ; Wait 5 µs
BF EWait_8
;