Datasheet

715
;
MOV.L #Wait10u,R3
MOV.L #FLMCR1,R0
OR.B #SWESET,@(R0,GBR) ; Set SWE
EWait_1 SUBC R2,R3 ; Wait 10 µs
BF EWait_1
;
MOV.L #0,R9 ; Initialize n (R9) to 0
;
MOV.B @(6,R5),R0
MOV.B R0,@(EBR1,GBR) ; Erase memory block (EBR1) setting
MOV.B @(7,R5),R0
MOV.B R0,@(EBR2,GBR) ; Erase memory block (EBR2) setting
;
MOV.L #FLMCR1,R0
MOV.L @R5,R6 ; Erase memory block start address -> R6
MOV.L #H’020000,R7
CMP/GT R6,R7
BT EraseLoop
MOV.L #FLMCR2,R0
;
EraseLoop .EQU $
MOV.L #WDT_TCSR,R1 ; Enable WDT
MOV.W #WDT_9m,R3 ; 9.2 ms cycle
MOV.W R3,@R1
;
MOV.L #Wait200u,R3
OR.B #ESUSET,@(R0,GBR) ; Set ESU
EWait_2 SUBC R2,R3 ; Wait 200 µs
BF EWait_2
;
MOV.L #Wait5m,R3
OR.B #ESET,@(R0,GBR) ; Set E
EWait_3 SUBC R2,R3 ; Wait 5 ms
BF EWait_3
;
MOV.L #Wait10u,R3