Datasheet

710
VerifyLoop .EQU $
MOV.L R11,@R12 ; Write H'FF to verify address
MOV.L R11,@R3 ; Reprogram data RAM (PdataBuff) initialization
MOV.L #Wait2u,R7
Wait_7 SUBC R2,R7 ; Wait 2 µs
BF Wait_7
;
MOV.L @R12+,R7
MOV.L @R1+,R8
CMP/EQ R7,R8 ; Verify
BT Verify_OK
MOV.L #1,R10 ; Verify NG, m <- 1
XOR R8,R7 ; Program data computation
NOT R7,R7
OR R7,R8
MOV.L R8,@R3 ; Store in reprogram data RAM (PdataBuff)
Verify_OK .EQU $
ADD.L #4,R3
ADD.L #-1,R13
CMP/PL R13
BT VerifyLoop
;
MOV.L #Wait4u,R7
AND.B #PVCLEAR,@(R0,GBR) ; Clear PV
Wait_8 SUBC R2,R7 ; Wait 4 µs
BF Wait_8
;
CMP/PL R10 ; if m=0 then GOTO Program_OK
BF Program_OK
ADD #1,R9
MOV.L #NG,R7 ; R7 <- NG (return value)
MOV.L #MAXVerify,R12 ; if n>=MAXVerify then Program NG
CMP/EQ R9,R12
BT Program_end
BRA Program_loop
NOP
Program_OK .EQU $