Datasheet

634
18.3.12 Port D Control Register L (PDCRL)
PDCRL is a 16-bit read/write register that selects the multiplexed pin functions for the least
significant sixteen port D pins. There are instances when these register settings will be ignored,
depending on the operation mode.
On-Chip ROM-Disabled Extended Mode:
• 144-pin version:
 Mode 0 (16-bit bus): Port D pins are data I/O pins; PDCRL settings are disabled.
 Mode 1 (32-bit bus): Port D pins are data I/O pins; PDCRL settings are disabled.
• 112-pin and 120-pin versions:
 Mode 0 (8-bit bus): Port D pins are data I/O pins; PDCRL settings are disabled.
 Mode 1 (16-bit bus): Port D pins are data I/O pins; PDCRL settings are disabled.
On-Chip ROM-Enabled Extended Mode: The port D pins are shared as data I/O pins and
general I/O pins; PDCRL settings are enabled.
Single Chip Mode: The port D pins are general I/O pins; PDCRL settings are disabled.
PDCRL is initialized to H'0000 by external power-on reset but is not initialized for manual resets,
reset by WDT, standby mode, or sleep mode, so the previous data is maintained.
Port D Control Register L (PDCRL)
Bit: 15 14 13 12 11 10 9 8
PD15
MD
PD14
MD
PD13
MD
PD12
MD
PD11
MD
PD10
MD
PD9
MD
PD8
MD
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
PD7
MD
PD6
MD
PD5
MD
PD4
MD
PD3
MD
PD2
MD
PD1
MD
PD0
MD
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W