Datasheet

628
Port D Control Register H1 (PDCRH1):
Bit: 15 14 13 12 11 10 9 8
PD31
MD1
PD31
MD0
PD30
MD1
PD30
MD0
PD29
MD1
PD29
MD0
PD28
MD1
PD28
MD0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7 6 5 4 3 2 1 0
PD27
MD1
PD27
MD0
PD26
MD1
PD26
MD0
PD25
MD1
PD25
MD0
PD24
MD1
PD24
MD0
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bits 15 and 14—PD31 Mode 1, 0 (PD31MD1 and PD31MD0): These bits select the function
of the PD31/D31/ADTRG pin.
Bit 15:
PD31MD1
Bit 14:
PD31MD0 Description
0 0 General input/output (PD31) (initial value) (No ROM, D31 with
CS0 = 32 bit width)
1 Data input/output (D31) (PD31 in single chip mode)
1 0 A/D conversion trigger input (ADTRG) (No ROM, D31 with
CS0 = 32 bit width)
1 Reserved
• Bits 13 and 12—PD30 Mode 1, 0 (PD30MD1 and PD30MD0): These bits select the function
of the PD30/D30/IRQOUT pin.
Bit 13:
PD30MD1
Bit 12:
PD30MD0 Description
0 0 General input/output (PD30) (initial value) (No ROM, D30 with
CS0 = 32 bit width)
1 Data input/output (D30) (PD30 in single chip mode)
1 0 Interrupt request received output (IRQOUT) (No ROM, D30
with CS0 = 32 bit width. Reserved in single chip mode)
1 Reserved