Datasheet

615
Port A Control Register L2 (PACRL2):
Bit: 15 14 13 12 11 10 9 8
PA7
MD1
PA7
MD0
PA6
MD1
PA6
MD0
PA5
MD1
PA5
MD0
— PA4MD
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R R/W
Bit: 7 6 5 4 3 2 1 0
— PA3MD PA2
MD1
PA2
MD0
— PA1MD — PA0MD
Initial value: 0 0 0 0 0 0 0 0
R/W: R R/W R/W R/W R R/W R R/W
• Bits 15 and 14—PA7 Mode 1, 0 (PA7MD1 and PA7MD0): These bits select the function of
the PA7/TCLKB/CS3 pin.
Bit 15:
PA7MD1
Bit 14:
PA7MD0 Description
0 0 General input/output (PA7) (initial value)
1 MTU timer clock input (TCLKB)
1 0 Chip select output (CS3) (PA7 in single chip mode)
1 Reserved
• Bits 13 and 12—PA6 Mode 1, 0 (PA6MD1 and PA6MD0): These bits select the function of
the PA6/TCLKA/CS2 pin.
Bit 13:
PA6MD1
Bit 12:
PA6MD0 Description
0 0 General input/output (PA6) (initial value)
1 MTU timer clock input (TCLKA)
1 0 Chip select output (CS2) (PA6 in single chip mode)
1 Reserved