Datasheet

595
CK
CMCNT
input clock
CMCNT
CMCOR
Compare
match signal
CMF
CMI
N
N
0
Figure 17.4 CMF Set Timing
17.4.3 Compare Match Flag Clear Timing
The CMF bit of the CMCSR register is cleared either by writing a 0 to it after reading a 1, or by a
clear signal after a DTC transfer. Figure 17.5 shows the timing when the CMF bit is cleared by the
CPU.
T
2
T
1
CK
CMF
CMCSR write cycle
Figure 17.5 Timing of CMF Clear by the CPU