Datasheet

591

17.2.2 Compare Match Timer Control/Status Register (CMCSR)

The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the

occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock

used for incrementation. It is initialized to H'0000 by power-on resets and by standby mode.

Manual reset does not initialize CMCSR.

Bit: 15 14 13 12 11 10 9 8

————————

Initial value: 0 0 0 0 0 0 0 0

R/W: R R R R R R R R

Bit: 7 6 5 4 3 2 1 0

CMF CMIE — — — — CKS1 CKS0

Initial value: 0 0 0 0 0 0 0 0

R/W: R/(W)

R/W R R R R R/W R/W

Note: * The only value that can be written is a 0 to clear the flag.

• Bits 15–8 and 5–2—Reserved: These bits always read as 0. The write value should always be

• Bit 7—Compare Match Flag (CMF): This flag indicates whether or not the CMCNT and

CMCOR values have matched.

Bit 7: CMF Description

0 CMCNT and CMCOR values have not matched (initial status)

Clear condition: Write a 0 to CMF after reading a 1 from it

1 CMCNT and CMCOR values have matched

• Bit 6—Compare Match Interrupt Enable (CMIE): Selects whether to enable or disable a

compare match interrupt (CMI) when the CMCNT and CMCOR values have matched (CMF =

1).

Bit 6: CMIE Description

0 Compare match interrupts (CMI) disabled (initial status)

1 Compare match interrupts (CMI) enabled