Datasheet
561
15.4.9 A/D Conversion Time
The high speed A/D converter has an on-chip sample and hold circuit. The high speed A/D
converter samples the input at time t
D
after the ADST bit is set to 1, and then starts the conversion.
The A/D conversion time t
CONV
is the sum of the conversion start delay time t
D
, the input sampling
time t
SPL
, and the operating time t
CP
. This conversion time is not a set value, but is decided by the
t
D
ADCSR write timing, or the timer conversion start trigger generation timing.
Figure 15.13 shows an example of A/D conversion timing. Table 15.7 lists A/D conversion times.
Address
Write signal
ADST
Sampling
timing
φ
ADF
t
D
t
CONV
t
SPL
t
CP
t
D
:
t
SPL
:
t
CONV
:
t
CP
:
A/D conversion start delay time
Input sampling time
A/D conversion time
Operation time
Figure 15.13 A/D Conversion Timing