Datasheet

470
14.1.2 Block Diagram
Figure 14.1 shows a block diagram of the SCI.
Parity
generation
Parity check
Transmit/
receive control
Baud rate 
generator
Clock
External clock
Bus interface
Internal

data bus
RxD
RDR TDR
RSR TSR
SSR
SCR
SMR
BRR
φ
φ/4
φ/16
φ/64
TEI
TxI
RxI
ERI
SCK
:
:
:
:
RSR
RDR
TSR
TDR
Receive shift register
Receive data register
Transmit shift register
Transmit data register
:
:
:
:
SMR
SCR
SSR
BRR
Serial mode register
Serial control register
Serial status register
Bit rate register
TxD
SCI
Module data bus
Figure 14.1 SCI Block Diagram