Datasheet
11
1.2 Block Diagram
Figure 1.1 is a block diagram of the SH7040 Series QFP-112 pin and TQFP-120 pin. Figure 1.2 is
a block diagram of the SH7040 Series QFP-144 pin.
PC15/A15
PC14/A14
PC13/A13
PC12/A12
PC11/A11
PC10/A10
PC9/A9
PC8/A8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
PD15/D15
PD14/D14
PD13/D13
PD12/D12
PD11/D11
PD10/D10
PD9/D9
PD8/D8
PD7/D7
PD6/D6
PD5/D5
PD4/D4
PD3/D3
PD2/D2
PD1/D1
PD0/D0
MD3
MD2
MD1
MD0
NMI
EXTAL
XTAL
V
CC
/FWP
*
1
V
CC
V
CC
PLLVCC
PLLCAP
PLLVSS
V
CC
V
CC
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
AV
CC
AV
SS
RES/V
PP
*
2
WDTOVF
PB9/IRQ7/A21/ADTRG
PB8/IRQ6/A20/WAIT
PB7/IRQ5/A19/BREQ
PB6/IRQ4/A18/BACK
PB5/IRQ3/POE3/RDWR
PB4/IRQ2/POE2/CASH
PB3/IRQ1/POE1/CASL
PB2/IRQ0/POE0/RAS
PB1/A17
PB0/A16
PA15/CK
PA14/RD
PA13/WRH
PA12/WRL
PA11/CS1
PA10/CS0
PA9/TCLKD/IRQ3
PA8/TCLKC/IRQ2
PA7/TCLKB/CS3
PA6/TCLKA/CS2
PA5/SCK1/DREQ1/IRQ
1
PA4/TXD1
PA3/RXD1
PA2/SCK0/DREQ0/IRQ
0
PA1/TXD0
PA0/RXD0
PE15/TIOC4D/DACK1/IRQOUT
PE14/TIOC4C/DACK0/AH
PE13/TIOC4B/MRES
PE12/TIOC4A
PE11/TIOC3D
PE10/TIOC3C
PE9/TIOC3B
PE8/TIOC3A
PE7/TIOC2B
PE6/TIOC2A
PE5/TIOC1B
PE4/TIOC1A
PE3/TIOC0D/DRAK1
PE2/TIOC0C/DREQ1
PE1/TIOC0B/DRAK0
PE0/TIOC0A/DREQ0
: Peripheral address bus
: Peripheral data bus
: Internal address bus
: Internal upper data bus
: Internal lower data bus
PLL
PF7/AN7
PF6/AN6
PF5/AN5
PF4/AN4
PF3/AN3
PF2/AN2
PF1/AN1
PF0/AN0
Flash ROM/PROM/
mask ROM
256kbytes/
128 kbytes/64 kbytes
RAM/cache
4 kbytes/1 kbyte
CPU
Data transfer
controller
Direct memory
access controller
Interrupt
controller
User
break
Bus state controller
Serial communi-
cation interface
(×2 channels)
Multifunction timer/
pulse unit
Compare match
timer (×2 channels)
A/D
converter
Watch-
dog
timer
V
SS
V
SS
V
SS
Notes: *1 V
CC
in the mask and ZTAT versions; FWP in the F-ZTAT version
(however, FWE in writer mode)
*2 V
pp
: ZTAT version only
Figure 1.1 Block Diagram of the SH7040, SH7042, SH7044 (QFP-112 Pin), SH7040, SH7042
(TQFP-120 pin)