Datasheet

459
• Bit 5—Timer Enable (TME): Enables or disables the timer.
Bit 5: TME Description
0 Timer disabled: TCNT is initialized to H'00 and count-up stops (initial
value)
1 Timer enabled: TCNT starts counting. A WDTOVF signal or interrupt is
generated when TCNT overflows.
• Bits 4 and 3—Reserved: These bits always read as 1. The write value should always be 1.
• Bits 2–0: Clock Select 2–0 (CKS2–CKS0): These bits select one of eight internal clock sources
for input to the TCNT. The clock signals are obtained by dividing the frequency of the system
clock (φ).
Description
Bit 2: CKS2 Bit 1: CKS1 Bit 0: CKS0 Clock Source
Overflow Interval
*
(φ = 28.7 MHz)
00 0 φ/2 (initial value) 17.9 µs
00 1 φ/64 573.4 µs
01 0 φ/128 1.1 ms
01 1 φ/256 2.3 ms
10 0 φ/512 4.6 ms
10 1 φ/1024 9.2 ms
11 0 φ/4096 36.7 ms
11 1 φ/8192 73.4 ms
Note: * The overflow interval listed is the time from when the TCNT begins counting at H'00 until
an overflow occurs.