Datasheet

398
T1 T1
H'FFFE H'FFFF N N + 1
H'FFFF
M
M
N
P
QP
M
Disabled
TCNT2 write data
TCNT2 address
TCNT write cycle
φ
Address
Write signal
TCNT2
TGR2A–B
Ch2 compare-
match signal A/B
TCNT1
input clock
TCNT1
TGR1A
Ch1 compare-
match signal A
TGR1B
Ch1 inputcapture
signal B

TCNT0
TGR0A–D
Ch0 input capture
signal A–D
Figure 12.85 TCNT2 Write and Overflow/Underflow Contention with Cascade Connection