Datasheet

396
12.7.8 Contention between Buffer Register Write and Input Capture
If an input capture signal is issued in the T
2
state of the buffer write cycle, write to the buffer
register does not occur, and buffer operation takes priority (figure 12.83).
TGR
Input capture
signal
TCNT
Address
Write signal
Buffer
re
g
ister
φ
T
1
T
2
Buffer register write cycle
Buffer register
address
N
MN
M
Figure 12.83 Buffer Register Write and Input Capture Contention