Datasheet

395
12.7.7 Contention between TGR Write and Input Capture
If an input capture signal is issued in the T
2
state of the TGR read cycle, input capture has priority,
and TGR write does not occur (figure 12.82).
TGR
Input capture
signal
TCNT
Address
Write signal
φ
T
1
T
2
TGR write cycle
TGR address
M
M
Figure 12.82 TGR Write and Input Capture Contention